In today's large SOCs that contain multiple compute cores, the cores can be running on different power domains (thus on separate PLLs) in order to gain full clock speed entitlement. However, there may be times when some of this compute power isn't necessary and could be powered down in order to reduce the overall power consumption of the device.
If the unit being powered down is a cache coherent master in a cache coherent interconnect system, the transition of the master into a fully powered down non-responsive state needs to be well understood by the rest of the system and the interconnect. With regards to snoop transactions, the power down transition needs to ensure that hang situations are avoided:    1) snoop transactions may be dropped because the interconnect has already sent snoop transactions to the master before the interconnect has knowledge that the master is powering down,    2) snoop responses may be dropped by the master if the power down mechanism doesn't anticipate that snoop transactions are still in the process of being serviced and simply powers down.
Memory Endian has typical been viewed as a Chip-Wide state. The entire chip has a single memory view that is aligned across all components in the system. As more individual processor cores have been added over time to make System on Chips (SOCs), where processors are individually attached to an interconnect and can each be running different code, the need for multi-endian views of the system memory has become necessary.
In a large scale System-on-Chip, the integration of multiple processors in a high performance device poses many additional challenges:
How to effectively integrate processors that support different protocols?
How to gain full processor performance and speed entitlement?
How to gain full code execution entitlement when there are multiple cores within a processor?
How to maintain memory coherency and synchronization between processors?
How to handle coherency when a processor is powered-down?
In a multi-core system, barrier transactions are used by a master to guarantee that ordering is maintained in the system interconnect. Memory barriers are used to guarantee a master's transactions are ordered correctly through an interconnect to a given endpoint. Synchronization Barriers are used to guarantee transaction visibility and ordering through the interconnect across multiple masters.
When a master issues these barrier transactions the interconnect needs to provide a barrier response signifying when the barrier request has been honored. If the interconnect lacks native support for barriers, the master effectively loses the ability to use barriers as a method of synchronizing its memory accesses or its accesses in relation to those of another master attached to the interconnect. If the interconnect does support barriers, tracking resources for barriers across multiple masters are finite and may not easily scale (with regards to resources, additional latency penalties, or complexity) as additional barrier-supporting masters are attached to the interconnect.